1. Field of the Invention
The present invention relates to a memory structure, and in particular, a dynamic random access memory (DRAM) and a memory array.
2. Description of Related Art
In respect of a memory, in order to access memory cells of the same word line in a non-obvious delay time, the structure of the word lines is often designed to be a stitch structure or a segment structure, as disclosed in U.S. Pat. Nos. 6,043,562 or 6,057,573. However, the above-mentioned structures need additional spaces to dispose stitch type word line contacts (stitch type WL contacts) and sub word line driver ICs. Therefore, although the access time is reduced, the chip size is increased. Thereby, the requirements of reducing the WL access time and miniaturizing the chip size can not be satisfied at the same time.